As the system operating voltages of modern integrated circuits (ICs) continue to decrease, the use of internal high voltage supply circuits is increasing. These internal high voltage supply circuits, which are typically referred to as “charge pumps”, are often utilized to provide high operating voltages during certain IC operations that require voltages higher than the system voltage. For example, in floating gate-type memory circuits, a charge pump is utilized to generate high programming voltages that are used during write operations to store a charge in a non-volatile memory cell of an IC device, such as electrically erasable/programmable read only memory (EEPROM) devices, or products of the microFLASH® technology family that are produced by the assignee of the present invention. In such applications, the charge pump is enabled during the high voltage (e.g., write/erase) operations, and then disabled during low voltage (e.g., read) operations.
When a charge pump is disabled, it is typically important to maintain the charge pump output terminal at the system operating voltage (or higher) to prevent voltage mismatch in the circuits connected to the charge pump output terminal. For example, when an IC includes one or more inverters connected to the charge pump output terminal, it is important to maintain the charge pump output at the system voltage when the charge pump is turned off to prevent these inverters from leaking.
FIG. 1 is a simplified schematic diagram showing a portion of an IC 10 including a conventional arrangement for maintaining an output terminal 21 of a charge pump 20 at a system voltage VDD when charge pump 20 is disabled. In particular, the conventional arrangement utilizes a PMOS transistor 30 connected between system voltage VDD and output terminal 21, with the gate of PMOS transistor 30 controlled by the charge pump enable control signal EN. In particular, when charge pump 20 is turned on (i.e., control signal EN is asserted, or high), charge pump 20 is turned on to generate an output voltage that is greater than system voltage VDD, and PMOS transistor 30 is turned off in an attempt to isolate output terminal 21 from system voltage source VDD. When charge pump 20 is subsequently turned off (control signal EN is de-asserted), the low (de-asserted) control signal EN turns on PMOS transistor 30, thereby connecting output terminal 21 to system voltage source VDD.
The conventional solution shown in FIG. 1 presents two problems.
First, when charge pump 20 is enabled, the voltage at the body (or bulk) B of PMOS transistor 30 must be as high as the source (S) side voltage (which is higher than system voltage VDD when charge pump 20 is enabled) in order to prevent a forward-biased diode between the source S and bulk B. However, as indicated in FIG. 1, the bulk B is typically tied to the drain D, which is maintained at VDD, so a forward-biased diode is typically generated that results in leakage of the charge pump output to the VDD source.
Second, in order to reliably maintain PMOS transistor 30 in a high impedance state while charge pump 20 is enabled, the control signal EN applied to the gate terminal of PMOS transistor 30 must be system voltage VDD or higher. However, control signal EN is often below system voltage VDD due to wire resistances and/or switching transistor drops, thereby resulting in leakage of the charge pump output to the VDD source while the charge pump is enabled.
What is needed is a voltage control circuit that reliably isolates a charge pump output terminal from the system voltage source when the charge pump is enabled, and reliably couples the charge pump output terminal to the system voltage source when the charge pump is disabled.